1. Field of the Invention
The present invention relates generally to flash memory cells in electrically erasable and programmable memory devices, and more particularly, to an array of flash memory cells with either a resistor coupled to the source or a positive voltage coupled to the source and with a negative voltage coupled to a substrate or p-well, to increase efficiency during an APDE (Automatic Program Disturb after Erase) process or during a programming process.
2. Discussion of the Related Art
One type of programmable memory cell is commonly referred to as a flash memory cell. The structure of one type of flash memory cell includes a source and a drain formed in a silicon substrate. The structure of another type of flash memory cell includes a source and a drain formed in a well that is formed in a silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of a flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as the tunnel oxide layer.
Prior programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such programming operations, the source and p-well or substrate of the flash memory cell are maintained at or near ground level in relation to the voltages applied to the control gate and drain.
Such a relatively high voltage potential applied between the drain and source causes electrons to flow through the channel region from the source to the drain. The electrons flowing between the source and drain can attain relatively high kinetic energy levels near the drain. In addition, the high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation, and a relatively high programming current in the cell being programmed results. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of a flash memory cell to cause conduction through the channel region during a read operation on the flash memory cell. The time involved in a programming operation depends upon the rate at which electrons are injected onto the floating gate. As can be appreciated, the slower the rate of injection the longer the programming time to reach the desired threshold voltage.
The microelectronic flash or block-erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory device of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor (FET) memory cells. Each of the FETs includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to read the cells, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell can be programmed by applying programming voltages as follows: a voltage, typically in the range of 8-10 volts to the control gate, a voltage in the range of 4 to 5.5 volts to the drain, grounding the source and grounding the substrate or p-well. As discussed above, these voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
In channel hot electron programming, hot electrons created by high lateral fields near the drain junction are injected into the floating gate. As discussed above, typical operating voltages for channel hot electron operation are: VD=4.0-5.5V, VG=8-10V, VSxcx9c0 V and Vsubxcx9c0 V. One of the limitations of channel hot electron programming for short channel NOR flash memory arrays is that the unselected cells sharing the same bitline begin to leak current when the high drain voltage is applied to the bitline. This leakage current Id is due to the Dibl (drain induced barrier lowering) effect in short channel devices. The combination of a large leakage current from the unselected cells and a large programming current from the selected cell being programmed results in unacceptably high total programming currents during device programming operation.
Therefore, what is needed is a method of programming to reduce or eliminate the leakage current for the unselected cells without decreasing the programming speed of the selected bit being programmed.
During the program or erase operations of a flash memory cell, charge carriers are injected into or tunnel out, respectively, of the floating gate structure of the flash memory cell. Such variation of the amount of charge carriers within the floating gate structure alters the threshold voltage of the flash memory cell, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure for an N-channel flash memory cell, the threshold voltage increases. Alternatively, when electrons are the charge carriers that tunnel out of the floating gate structure, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell, as known to one of ordinary skill in the art of electronics.
During erasing of the flash memory cells of the array of flash memory cells, charge carriers such as electrons are pulled out of the respective floating gate structure of each flash memory cell to decrease the threshold voltage of each flash memory cell. Typically, same bias voltages are applied at terminals of each of the flash memory cells of the array during this erase process. However, because of variations in the structures of each of the flash memory cells, variations in threshold voltage result across the array of flash memory cells after the erase process, as known to one of ordinary skill in the art of flash memory technology. Thus, some flash memory cells that are xe2x80x9cover-erasedxe2x80x9d in the array attain a lower threshold voltage than desired. A flash memory cell with a lower threshold voltage undesirably has higher leakage current.
An APDE (Automatic Program Disturb after Erase) process corrects for such over-erased flash memory cells, as known to one of ordinary skill in the art of flash memory technology. During such an APDE process, sufficient charge carriers such as electrons are reinjected into the floating gate structure of each flash memory cell of the array after an erase process to restore the threshold voltage of the over-erased flash memory cells.
Referring to FIG. 11, a circuit diagram of a column of array of flash memory cells having 512 rows is illustrated. A first flash memory cell 252 represents one flash memory cell in the column of 512 flash memory cells, and a second flash memory cell 254 represents the other 511 flash memory cells coupled in parallel in the column of 512 flash memory cells. A resistor 258 represents the effective resistance of a pass transistor coupled between the bit line and the drain terminals of the column of flash memory cells. A source resistor 260 is coupled to the source of the flash memory cells. The source terminals of each flash memory cell of a column are coupled together and to a respective source resistor.
During an APDE (Automatic Program Disturb after Erase) process, a bit line APDE (Automatic Program Disturb after Erase) voltage of about 5 Volts provided by a bit line voltage source 262 is applied on the bit line coupled to each drain terminal of the 512 flash memory cells in the column. In addition, a control gate APDE (Automatic Program Disturb after Erase) voltage of about 0.5 Volts provided by a control gate voltage source 264 is applied on each control gate terminal of the 512 flash memory cells in the column. Furthermore, for the APDE process, the source resistor 260 is coupled between the source of each flash memory cell and the ground node 256. Furthermore, in the prior art, each substrate or p-well terminal of the 512 flash memory cells in the column is coupled to the ground node 256 having about 0 Volts during the APDE process. When the flash memory cells are comprised of N-channel flash memory cells, the substrate is a p-well being doped with a P-type dopant.
Referring to FIG. 11, such biases are applied to the column of 512 flash memory cells for a predetermined time period to inject a particular amount of charge carriers such as electrons into the floating gate structure of each flash memory cell to raise the threshold voltage of each flash memory cell in the column of 512 flash memory cells. The longer the time period for applying such bias, the higher the increase in the threshold voltage of each flash memory cell. The higher the threshold voltage of each flash memory cell, the lower the leakage current through each flash memory cell. Such a time period for applying the bias for the APDE (Automatic Program Disturb after Erase) process is termed the xe2x80x9cAPDxe2x80x9d time in the field of flash memory technology.
Further referring to FIG. 11, the first flash memory cell 252 represents the one flash memory cell, of the column of 512 flash memory cells, having a fastest rate of increase in threshold voltage to retain the desired threshold voltage in a shortest time period. The length of the time period for the flash memory cell 252 attaining the desired threshold voltage is affected by the leakage current of the other 511 flash cells 254 in the column of flash memory cells, Ileak.
Such leakage current is disadvantageous because with such leakage current flowing through the resistors 258 and 260 coupled at the drain and source terminals of the flash memory cells, the resulting voltage across the drain and source terminals of the flash memory cells are lowered. Such lowered voltage across the drain and source terminals decreases the rate of charge carrier injection into the floating gate structure of the flash memory cells for a less efficient APDE (Automatic Program Disturb after Erase) process.
The level of leakage current Ileak is especially acute for flash memory cells having scaled down dimensions of hundreds of nanometers for the channel length because of DIBL (Drain Induced Barrier Lowering). For example, when the channel length of each flash memory cell is less than about 0.22 xcexcm, the DIBL (Drain Induced Barrier Lowering) voltage change at the drain of a flash memory may be greater than about 0.6 Volts. Despite higher leakage current Ileak with a smaller flash memory cell, the dimensions of the flash memory cell are desired to be scaled down further for enhanced speed performance and smaller occupied IC area, as known to one of ordinary skill in the art of flash memory technology.
Applying the voltage biases of the APDE (Automatic Program Disturb after Erase) process for a longer period of time (i.e., a higher APD time) ensures a higher average threshold voltage for the column of flash memory cells to minimize leakage current. A predetermined APD time is used for each cycle in the APDE process such that an acceptably low level of leakage current flows through the column of flash memory cells. However, a higher APD time disadvantageously slows down the erasing cycle of the flash memory array.
Thus, a mechanism is desired for minimizing the APD time to achieve an acceptably low level of leakage current flowing through the column of flash memory cells during the APDE (Automatic Program Disturb after Erase) process.
Accordingly, in a general aspect of the present invention, a source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during the APDE (Automatic Program Disturb after Erase) process.
In one embodiment of the present invention, an array of multiple flash memory cells is formed in rows and columns, and a flash memory cell is located at each intersection of a column and a row. Each flash memory cell has a control gate and a floating gate formed over a substrate, and each flash memory cell has a source and a drain formed in the substrate. Each of the drains of the flash memory cells in a column are coupled together as a common bit line terminal. Additionally, each of the sources of the flash memory cells in a column are coupled together as a common source terminal. Furthermore, each of the substrates of the flash memory cells in a column are coupled together as a common substrate terminal.
In a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. A source resistor is coupled to the common source terminal to which the source of the selected flash memory cell is connected. A substrate programming voltage that is a negative voltage is applied to the substrate or p-well of the selected flash memory cell.
The present invention may be used to particular advantage when the flash memory cells are comprised of N-channel field effect transistors, when the substrate programming voltage applied on the substrate of the selected flash memory cell is in a range of from about negative 3 Volts to about negative 0.5 volts, and when the source resistor has a resistance value in a range of from about 2 kilo-ohms to about 50 kilo-ohms, and when the drain voltage is greater than about 4.0 Volts, according to one embodiment of the present invention.
In a system and method for performing an APDE (automatic program disturb after erase) process in the flash memory device according to another embodiment of the present invention, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A control gate APDE (automatic program disturb after erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. A bit line APDE (automatic program disturb after erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A source resistor is coupled to the common source terminal corresponding to the selected column of flash memory cells. A substrate APDE (automatic program disturb after erase) voltage that is a negative voltage is applied to the common substrate or p-well terminal corresponding to the selected column of flash memory cells.
In another system and method for performing an APDE (automatic program disturb after erase) process in the flash memory device according to a further embodiment of the present invention, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A control gate APDE (automatic program disturb after erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. A bit line APDE (automatic program disturb after erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A source APDE (automatic program disturb after erase) voltage that is a positive voltage is applied to the common source terminal corresponding to the selected column of flash memory cells. A substrate APDE (automatic program disturb after erase) voltage that is a negative voltage is applied to the common substrate or p-well terminal corresponding to the selected column of flash memory cells.
The present invention may be used to particular advantage when the source is coupled to the control gate for each flash memory cell in a self-biasing configuration during the APDE process such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.
In this manner, the voltage formed at the source resistor or the source voltage applied to the source of the flash memory cell minimizes leakage current through a column of flash memory cells during the programming or APDE process. On the other hand, the negative substrate or p-well voltage enhances the lateral field in the channels of the column of flash memory cells to enhance the speed performance of the flash memory cells during the programming or APDE process.